RADAR PROCESSING WITH TIGER-SHARC BOARDS(2007-2010)
SYSTEM: 3D radar employed for aerial discovery of surfaces and research and designation of targets in antiaircraft systems at short and medium range. The radar is provided with a multifunctional architecture, with an active phased array antenna whose beam is adjustable both in azimuth and in elevation. It is capable of high performances either in surveillance or in tracking.
DSP SOFTWARE: The signal processing input data flow consists of four sigma channels, one omega channel (omni-directional, used for jamming filtering), azimuth delta and elevation delta beams (for accurate estimation of the targets position). The radar multifunctional architecture requires that signal processing is able to process in real-time, and with strict latency requirements, different kinds of bursts in an unexpected sequence. The processing variability affects both the sweep length, tied to the observation range, and the sweep number composing the burst, tied to the Doppler analysis resolution. The sigma channel processing (narrow beam) consists of DDC (Digital Down Conversion) and DPC (Digital Pulse Compression) for each sweep, RTWS (Real Time Weight Selection = clutter estimation and characterization), MTD (Moving Target Detection = Doppler Analysis) applied to the burst, threshold computing utilizing CFAR algorithms (Constant False Alarm Rate) OSGO/CAGO, thresholds application and target reports production. In correspondence at the identified targets, the sigma channel is finally compared with the signal supplied by omega and delta channels (after application of DDC, DPC and MTD processing), with the purpose to filter out jammers and to accurately compute the kind and position of the targets.
DSP HARDWARE: The DSP hardware consists of two boards Bittware TS6U (Tiger-6U-cPCI, Octal ADSP-TS101S Tiger SHARC 6U cPCI board). The TS6U is configured with eight ADSP-TS101S Tiger SHARC DSPs, arranged in two clusters of four processors and 256 Mbytes of SDRAM, and a Xilinx Virtex-II reconfigurable FPGA. Each Tiger SHARC DSP has four 250 Mbytes/sec link ports allowing high-speed communication between Tiger SHARC DSP either on the same card or on other cards, and provides 6 Mbits of on-chip SRAM and 1.5 GFLOPS (32-bit floating point) or 6 GOPS (16-bit fixed point) of processing power. For the two boards, the total DSP processing power is 24 GFLOPS for the 16 TS101, plus the computational power of two Xilinx Virtex-II FPGAs.
Defence