ASU 2 EMULATOR (2006)
In-house implementation of an antenna simulator able to receive 4 Hot-Link channels managing them in real-time. Every channel transmits a digital buffer of about 100 bit with a minimum delay of 1 ms. The management of the fast digital signals is carried out via alpha-data boards using a FPGA Xilinx Virtex IV.
The system, besides accomplishing various control tasks on the received signals, can store the whole acquired information on magnetic media.
Defence